Vlsi design
Previous year question paper with solutions for Vlsi design
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- What is entity?
- What is use of process in VHDL?
- Explain the term generic.
- Write the VHDL code using case statement.
- What do you understand by the term threshold voltage?
- What are the various CAD tool available in digital circuit design?
- Differentiate between synthesis and simulation.
- Differentiate between package and library.
- What are object types involved in VHDL?
- State the advantages of VHDL.
- Give an example of concurrent and sequential signal assignment.
- Explain basic difference between function and procedure.
- What are various sources of power dissipation in CMOS circuits?
- What are test benches?
- What is the difference between synthesis and simulation?
- With examples explain how different architectures can be declared under a single entity.
- Explain different types of delays in VHDL.
- Differentiate between decoder and demultiplexer.
- What do you mean by package and library?
- Explain VHDL design flow with an example.
- What is power dissipation
- Write the VHDL code for half adder
- Describe if else statement
- Differentiate between library and package
- Write and explain VHDL code using CASE statement
- Differentiate between signal and variable
- How is generic statement useful in VHDL code
- What are PULL UP and PULL DOWN networks
- Compare between function and procedure
- Explain the types of delays in VHDL